The mainboard has five M.2 slots. Of these, the M.2_2 and M.2_3 slots are shared with the GPU bandwidth, which means that the primary PCIe graphics card is reduced from x16 to x8 lanes when these slots are used. The M.2_1 slot, on the other hand, is connected directly to the CPU and does not share its lanes with the GPU. The M.2_4 and M.2_5 slots are connected via the chipset and run with PCIe 4.0 x4, but do not share lanes with the GPU.

To summarise: There is at least one M.2 slot (M.2_1) that does not share lanes with the GPU.

In the product, the primary PCIe x16 slot is directly connected to the CPU and receives full x16 lanes as long as no M.2 SSD is used in a slot that shares these lanes (e.g. M.2_2 or M.2_3). The remaining PCIe slots are connected via the chipset and share the bandwidth with each other, but not with the primary GPU slot. The GPU lanes are therefore only restricted if certain M.2 slots are used in parallel.

The Pcie slots share the bandwidth with the gpu